Features
			
 
			
• Cost effective, single chip, 8-port ATM IMA and UNI processor.
			
• Up to 4 IMA groups over 8 T1/E1 links can be implemented.
			
• Supports MIXED mode; links not assigned to an IMA group can be used in UNI mode.
			
• Versatile PCM Interface to most popular T1 or E1 framers, reducing development time.
			
• Supports Symmetrical and Asymmetrical Operation.
			
• Supports both Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) clocking modes.
			
• Supports T1 ISDN lines.
			
• Provides UTOPIA Level 2 MPHY Interface (MT90220 device slaved to ATM device).
			
• Complies with ITU G.804 recommendations for performing cell mapping into T1 and E1 transmission systems.
			
• Provides ATM framing using cell delineation according to the ITU I.432 cell delineation process.
			
			
• Provides Header Error Control (HEC) verification and generation, error detection, Filler cell filtering (IMA mode) and Idle/ Unassigned cell filtering (UNI mode).
			
• Provides statistics to support MIB.
			
• Connects to popular asychronous SRAM.
			
• Provides statistics on the number of HEC errors.
			
• 8 bit Microprocessor Interface, compatible with Intel and Motorola
			
• 3.3V operation / 5V tolerant inputs.
			
• MQFP-208 pin.
			
• JTAG Test support.